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? semiconductor components industries, llc, 2010 february, 2010 ? rev. 13 1 publication order number: ncp5351/d ncp5351 4 a synchronous buck power mosfet driver the ncp5351 is a dual mosfet gate driver optimized to drive the gates of both high ? side and low ? side power mosfets in a synchronous buck converter. the ncp5351 is an excellent companion to multiphase controllers that do not have integrated gate drivers, such as on semiconductor?s cs5323, cs5305 or cs5307. this architecture provides a power supply designer the flexibility to locate the gate drivers close to the mosfets. the 4.0 a drive capability makes the ncp5351 ideal for minimizing switching losses in mosfets with large input capacitance. optimized internal, adaptive nonoverlap circuitry further reduces switching losses by preventing simultaneous conduction of both mosfets. the floating top driver design can accommodate mosfet drain voltages as high as 25 v. both gate outputs can be driven low, and supply current reduced to less than 25 a, by applying a low logic level to the enable (en) pin. an undervoltage lockout function ensures that both driver outputs are low when the supply voltage is low, and a thermal shutdown function provides the ic with overtemperature protection. the ncp5351 is pin ? to ? pin compatible with the sc1205 and is available in a standard so ? 8 package and thermally enhanced dfn10. features ? 4.0 a peak drive current ? rise and fall times < 15 ns typical into 6000 pf ? propagation delay from inputs to outputs < 20 ns ? adaptive nonoverlap time optimized for large power mosfets ? floating top driver accommodates applications up to 25 v ? undervoltage lockout to prevent switching when the input voltage is low ? thermal shutdown protection against overtemperature ? < 1.0 ma quiescent current ? enabled ? 25 a quiescent current ? disabled ? internal tg to drn pulldown resistor prevents hv supply ? induced turn on of high ? side mosfet ? pb ? free package is available a = assembly location l = wafer lot y = year w = work week = pb ? free package marking diagrams pin connections so ? 8 d suffix case 751 en co 18 v s bst bg tg pgnd drn http://onsemi.com 1 8 dfn10 mn suffix case 485c 5351 alyw 1 drn tg n/c bst co gnd bg en 110 dfn10 so ? 8 1 n/c v s 5351 alyw 1 8 (note: microdot may be in either location) see detailed ordering and shipping information in the package dimensions section on p age 12 of this data sheet. ordering information
ncp5351 http://onsemi.com 2 figure 1. block diagram + ? v s nonoverlap control + ? thermal shutdown en co pgnd level shifter delay delay + ? v s 4.25 v 4.0 v bg drn tg bst table 1. input ? output truth table en co drn tg bg l x x l l h l < 3.0 v l h h h < 3.0 v h l h l > 5.0 v l l h h > 5.0 v h l figure 2. timing diagram tpdl bg tpdh bg (nonoverlap) tpdl tg tf bg tf tg tr bg tr tg tpdh tg (nonoverlap) 4.0 v v co v tg ? v drn v bg v drn
ncp5351 http://onsemi.com 3 package pin description pin number pin symbol description so ? 8 dfn ? 10 1 1 drn the switching node common to the high and low ? side fets. the high ? side (tg) driver and supply (bst) are referenced to this pin. 2 2 tg driver output to the high ? side mosfet gate. 3 4 bst bootstrap supply voltage input. in conjunction with a schottky diode to v s , a 0.1 f to 1.0 f ceramic capacitor connected between bst and drn develops supply voltage for the high ? side driver (tg). 4 5 co logic level control input produces complementary output states ? no inversion at tg; inversion at bg. ? 3, 8 n/c not connected. 5 6 en logic level enable input forces tg and bg low, and supply current to 10 a when en is low. 6 7 v s power supply input. a 0.1 f to 1.0 f ceramic capacitor should be connected from this pin to pgnd. 7 9 bg driver output to the low ? side (synchronous rectifier) mosfet gate. 8 ? pgnd ground. ? 10 gnd ground.
ncp5351 http://onsemi.com 4 maximum ratings ? so ? 8 rating value unit operating junction temperature, t j internally limited c package thermal resistance: so ? 8 junction ? to ? case, r jc junction ? to ? ambient, r ja 45 165 c/w c/w storage temperature range, t s ? 65 to 150 c lead temperature soldering: reflow: (smd styles only) (note 1) pb ? free 230 peak 260 peak c msl rating 1 ? stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. note: this device is esd sensitive. use standard esd precautions when handling. 1. 60 seconds maximum above 183 c. maximum ratings ? dfn ? 10 rating symbol value unit thermal resistance, junction ? to ? air r ja 68.5 c/w operating ambient temperature range t a ? 30 to 85 c esd withstand voltage human body model (note 2) machine model (note 2) v esd > 2500 > 150 v moisture sensitivity msl level 1 storage temperature range t stg ? 55 to 150 c junction operating temperature t j ? 30 to 125 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 2. this device series contains esd protection and exceeds the following tests: human body model, 100 pf discharge through a 1.5 k following specification jesd22/a114. machine model, 200 pf discharged through all pins following specification jesd22/a115. latchup as per jesd78 class ii: > 100 ma. maximum ratings pin symbol pin name v max v min i source i sink v s main supply voltage input 6.3 v ? 0.3 v na 4.0 a peak (< 100 s) 250 ma dc bst bootstrap supply voltage input 25 v wrt/pgnd 6.3 v wrt/drn ? 0.3 v wrt/drn na 4.0 a peak (< 100 s) 250 ma dc drn switching node (bootstrap supply return) 25 v ? 1.0 v dc ? 5.0 v for 100 ns ? 6.0 v for 20 ns 4.0 a peak (< 100 s) 250 ma dc na tg high ? side driver output (top gate) 25 v wrt/pgnd 6.3 v wrt/drn ? 0.3 v wrt/drn 4.0 a peak (< 100 s) 250 ma dc 4.0 a peak (< 100 s) 250 ma dc bg low ? side driver output (bottom gate) 6.3 v ? 0.3 v 4.0 a peak (< 100 s) 250 ma dc 4.0 a peak (< 100 s) 250 ma dc co tg & bg control input 6.3 v ? 0.3 v 1.0 ma 1.0 ma en enable input 6.3 v ? 0.3 v 1.0 ma 1.0 ma pgnd ground 0 v 0 v 4.0 a peak (< 100 s) 250 ma dc na note: all voltages are with respect to pgnd except where noted.
ncp5351 http://onsemi.com 5 electrical characteristics (0 c < t j < 125 c; v s = 5.0 v; 4.0 v < v bst < 25 v; v en = v s ; unless otherwise noted) parameter test conditions min typ max unit dc operating specifications power supply v s quiescent current, operating v co = 0 v, 4.5 v; no output switching ? 1.0 ? ma v bst quiescent current, operat- ing v co = 0 v, 4.5 v; no output switching ? 50 ? a quiescent current, non ? operat- ing v en = 0 v; v co = 0 v, 4.5 v ? ? 25 a undervoltage lockout start threshold co = 0 v 4.05 4.25 4.48 v hysteresis co = 0 v ? 275 ? mv co input characteristics high threshold ? 2.0 ? ? v low threshold ? ? ? 0.8 v input bias current 0 < v co < v s ? 0 1.0 a en input characteristics high threshold both outputs respond to co 2.0 ? ? v low threshold both outputs are low, independent of co ? ? 0.8 v input bias current 0 < v en < v s ? 0 10 a thermal shutdown overtemperature trip point ? ? 170 ? c hysteresis ? ? 30 ? c high ? side driver peak output current ? ? 4.0 ? a output resistance (sourcing) duty cycle < 2.0%, pulse width < 100 s, t j = 125 c, v bst ? v drn = 4.5 v, v tg = 4.0 v + v drn ? 0.5 ? output resistance (sinking) duty cycle < 2.0%, pulse width < 100 s, t j = 125 c, v bst ? v drn = 4.5 v, v tg = 0.5 v + v drn ? 0.42 ? low ? side driver peak output current ? ? 4.0 ? a output resistance (sourcing) duty cycle < 2.0%, pulse width < 100 s, t j = 125 c, v s = 4.5 v, v bg = 4.0 v ? 0.6 ? output resistance (sinking) duty cycle < 2.0%, pulse width < 100 s, t j = 125 c, v s = 4.5 v, v bg = 0.5 v ? 0.42 ?
ncp5351 http://onsemi.com 6 electrical characteristics (continued) (0 c < t j < 125 c; v s = 5.0 v; 4.0 v < v bst < 25 v; v en = v s , c load = 5.7 nf; unless otherwise noted.) parameter test conditions min typ max unit ac operating specifications high ? side driver rise time v bst ? v drn = 5.0 v, t j = 125 c ? 8.0 16 ns fall time v bst ? v drn = 5.0 v, t j = 125 c ? 14 21 ns propagation delay time, tg going high (nonoverlap time) v bst ? v drn = 5.0 v, t j = 125 c 30 45 60 ns propagation delay time, tg going low v bst ? v drn = 5.0 v, t j = 125 c ? 18 37 ns low ? side driver rise time t j = 125 c ? 10 15 ns fall time t j = 125 c ? 12 20 ns propagation delay time, bg going high (non ? overlap time) t j = 125 c 25 55 80 ns propagation delay time, bg going low t j = 125 c ? 10 18 ns undervoltage lockout v s rising en = v s , co = 0 v, dv s /dt > 1.0 v/ s, from 4.0 v to 4.5 v, time to bg > 1.0 v, t j = 125 c ? 30 ? s v s falling en = v s , co = 0 v, dv s /dt < ? 1.0 v/ s, from 4.5 v to 4.0 v, time to bg < 1.0 v, t j = 125 c ? 500 ? s
ncp5351 http://onsemi.com 7 figure 3. application diagram v id2 v id3 v id4 pwrls v ffb ss pwrgd drvon i lim r osc v cc gate1 gate2 gate3 gate4 gnd v id1 v id0 v id5 enable cs2n cs2p cs1n cs1p sgnd v drp v fb comp cs4n cs4p cs3n cs3p 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 pwrgd 3.3 v v id4 v id3 v id2 v id1 v id0 v id5 enable 3.3 v v s co en pgnd bst tg drn bg ncp5351 3 2 1 7 6 4 5 8 12 v 5.0 v atx 12 v v s co en pgnd bst tg drn bg ncp5351 3 2 1 7 6 4 5 8 v s co en pgnd bst tg drn bg ncp5351 3 2 1 7 6 4 5 8 v s co en pgnd bst tg drn bg ncp5351 3 2 1 7 6 4 5 8 + + v core gnd ntc near inductor sgnd near socket v ffb connection ncp5314
ncp5351 http://onsemi.com 8 applications information theory of operation enable pin the enable pin (en) is controlled by a logic level input. with a logic level high on the en pin, the output states of the drivers are controlled by applying a logic level voltage to the co pin. with a logic level low both gates are forced low. by bringing both gates low when disabling, the output voltage is prevented from ringing below ground, which could potentially cause damage to the microprocessor or the device being powered. undervoltage lockout the tg and bg are held low until v s reaches 4.25 v during startup. the co pin takes control of the gates? states when the v s threshold is exceeded. if v s decreases 300 mv below threshold, the output gate will be forced low and remain low until v s rises above startup threshold. adaptive nonoverlap the adaptive nonoverlap prevents a condition where the top and bottom mosfets conduct at the same time and short the input supply. when the top mosfet is turning off, the drain (switch node) is sampled and the bg is disabled for a fixed delay time (tpdh bg ) after the drain drops below 4 v, thus eliminating the possibility of shoot ? through. when the bottom mosfet is turning off, tg is disabled for a fixed delay (tpdh tg ) after bg drops below 2.0 v. (see figure 2 for complete timing information). layout guidelines when designing any switching regulator, the layout is very important for proper operation. the designer should follow some simple layout guidelines when incorporating gate drivers in their designs. gate drives experience high di/dt during switching and the inductance of gate drive traces should be minimized. gate drive traces should be kept as short and wide as practical and should have a return path directly below the gate trace. the use of a ground plane is a desirable way to return ground signals. also, component location will make a difference. the boost and the v s capacitor are the most critical and should be placed as close as possible to the driver ic pins, as shown in figure 4(a), c21 and c17. c17 1.0 f r33 2.2 gate driver (a) ncp5351 en v s bg pgnd co bst tg drn 5 6 7 8 4 3 2 1 gate1 drvon 5 v c21 1.0 f d32 bat54 u3 12 v q7 80no2 q9 80no2 (b) figure 4. proper layout (a), component selection (b)
ncp5351 http://onsemi.com 9 typical performance characteristics conditions: bst ? drn = 5.0 v; room temperature; oscilloscope referenced to v s (5.0 v). figure 5. top gate sinking current from 0.108 figure 6. top gate sinking conditions: v s = 5.0 v; room temperature; co = 0 v. figure 7. bottom gate sinking current from 0.108 figure 8. bottom gate sinking 0 v 0 v ? 5.0 v ? 5.0 v co tg 0 v ? 5.0 v input pulse 50 ns ? 3.5 v 0 v ? 4.5 v ? 0.5 v drn bg ? 3.5 v ? 4.5 v input pulse 50 ns v s bst pgnd drn en co tg bg ncp5351 ? 5.0 v r1 1.0 k measurement r2* 0.108 *applied after power up and input. c4 100 nf c3 100 nf c2 1.0 f c1 1.0 f com hot v s pgnd co en bst tg bg ncp5351 ? 5.0 v r1 1.0 k measurement r2* 0.108 *applied after power up and input. c1 1.0 f com hot drn r3 50 c2 1.0 f
ncp5351 http://onsemi.com 10 typical performance characteristics conditions: v s = 5.0 v; room temperature; drn = 0 v. figure 9. bottom gate sourcing current into 0.108 figure 10. bottom gate sourcing figure 11. top gate sourcing current into 0.108 figure 12. top gate sourcing 0 0 co bg +5.0 v 0 v input pulse 50 ns +5.0 v 0 v input pulse 50 ns 0 0 co tg conditions: bst ? drn = 5.0 v; room temperature; drn = 0 v. v s bst pgnd drn en co tg bg ncp5351 +5.0 v r1 1.0 k measurement r2* 0.108 *applied after power up and input. c4 100 nf c3 100 nf c2 1.0 f c1 1.0 f + ? v s bst pgnd drn en co tg bg ncp5351 +5.0 v r1 1.0 k measurement r2* 0.108 *applied after power up and input. c4 100 nf c3 100 nf c2 1.0 f c1 1.0 f + ?
ncp5351 http://onsemi.com 11 typical performance characteristics figure 13. nonoverlap test configuration v s pgnd en co bst tg drn bg ncp5351 +5.0 v measurements c3 100 nf c1 10 f input pulse + ? r1 1.0 k c2 10 f r2 50 c4 100 nf + ? gated pulse burst (2) tpdh bg (non ? overlap) tpdh tg (non ? overlap) drn co tg bg tpdl bg tpdl tg 4.0 v conditions: v s = 5.0 v; bst ? drn = 5.0 v; c load = 5.7 nf; room temperature. figure 14. top gate rise time figure 15. top gate fall time conditions: v s = 5.0 v; bst ? drn = 5.0 v; c load = 5.7 nf; room temperature.
ncp5351 http://onsemi.com 12 typical performance characteristics conditions: v s = 5.0 v; bst ? drn = 5.0 v; c load = 5.7 nf; room temperature. figure 16. bottom gate fall time figure 17. bottom gate rise time conditions: v s = 5.0 v; bst ? drn = 5.0 v; c load = 5.7 nf; room temperature. figure 18. bottom gate and top gate rise/fall time test v s bst pgnd drn en co tg bg ncp5351 +5.0 v measurements c4 5.7 nf c3 5.7 nf c2 100 nf c1 100 nf +5.0 v 0 v input pulse 60 ns + ? ordering information device package shipping ? ncp5351d soic ? 8 98 units / rail ncp5351dg soic ? 8 (pb ? free) 98 units / rail ncp5351dr2 soic ? 8 2500 / tape & reel NCP5351DR2G soic ? 8 (pb ? free) 2500 / tape & reel ncp5351mnr2 dfn10 2500 / tape & reel ncp5351mnr2g dfn10 (pb ? free) 2500 / tape & reel ? for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp5351 http://onsemi.com 13 package dimensions dfn10, 3x3, 0.5p case 485c ? 01 issue b 10x seating plane l d e 0.15 c a a1 e d2 e2 b 15 10 6 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. terminal b may have mold compound material along side edge. mold flashing may not exceed 30 microns onto bottom surface of terminal b. 6. details a and b show optional views for end of terminal lead at edge of package. ??? ??? ??? ??? b a 0.15 c top view side view bottom view pin 1 reference 0.10 c 0.08 c (a3) c 10x 10x 0.10 c 0.05 c a b note 3 k 10x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 2.40 2.60 e 3.00 bsc e2 1.70 1.90 e 0.50 bsc l 0.35 0.45 l1 0.00 0.03 detail a k 0.19 typ 2x 2x l1 detail a bottom view (optional) *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2.1746 2.6016 1.8508 0.5000 pitch 0.5651 10x 3.3048 0.3008 10x dimensions: millimeters
ncp5351 http://onsemi.com 14 package dimensions soic ? 8 nb case 751 ? 07 issue aj seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. ncp5351/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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